The present invention relates generally to direct memory access (DMA) controllers, and in particular, to DMA controllers for use with external interfaces.
DMA controllers are used for controlling the communication between external devices and a processor and memory. The DMA controller can control direct memory access to and from external serial devices such as those serial devices serviced by RS232, RS422, and RS485 serial interfaces. The DMA controller controls the parallel data communication between a module bus, which communicates with the processor and the memory, and an input/output (I/O) bus, which communicates with serial devices. Since the DMA controller provides parallel data on the I/O bus, a universal asynchronous receiver/transmitter (UART) is typically coupled between the I/O bus and the serial device to provide translation between serial data provided by the serial device and parallel data provided by the DMA controller on the I/O bus. The UART is a standard component used to receive data from and transmit data to a serial device from a parallel data bus.
Input data received by a UART from a serial device will be lost in a system not using a DMA controller if the input data is not read by the processor before the next byte of data arrives. To solve this problem, many UARTs contain a first in-first out (FIFO) buffer. The FIFO buffer provides additional storage for the input data provided by a serial device to make room for the next byte of data until the processor, in the absence of a DMA controller, is free to read the data from the serial device. However, the processor needs to be interrupted to read the data from the UART's FIFO and transfer it to main memory. Thus, DMA controllers are commonly utilized in computer systems comprising a plurality of UARTs, because DMA controllers write input data directly to the processor's memory without interrupting the processor. Therefore, the DMA controller in effect acts to expand the storage of input data from a serial device before the input data is actually processed by the processor. Another reason that DMA controllers are used in computer systems comprising UARTs is that DMA controllers switch from one active UART device to another active UART device in significantly less time than if the software that operates the processor controls the switching between the UART devices because of the time overhead of software operations as compared to hardware logic gates used in the DMA controller.
As mentioned above, the UART usually includes a FIFO buffer memory for storing serial device input data that has been translated into parallel form data by the UART. Typically, the FIFO is 16 bytes deep. A problem exists in using the 16 byte deep FIFO in a multi-tasking software environment because several tasks can be active at the same time, and additional tasks are activated when the processor is interrupted. The FIFO needs to be capable of storing more than 16 bytes to guarantee that no data will be lost during the delays and added processing times arising in this multi-tasking environment. Since a single processor typically performs operations with respect to a single task at a time, software controlling the processor implements a time division multiplexed and/or priority multiplexed scheme. In such multiplexing schemes, the software controls the processor to allow the processor to process one task for a selected amount of time or until a higher priority task request is received. In either case, the software saves the state of the current task and switches to the next task in time or to a higher priority task. If many tasks are active, or if a few high priority tasks are active, some tasks are not revisited for further processing by the processor for a relatively long time. In addition, as the number of active tasks increases, or when more high-priority tasks are active, the delay from one processing of a particular task to the next processing of the same task can increase significantly. If this delay from one processing to the next processing is too long, the FIFO buffer will lose data associated with some I/O tasks if the FIFO is not deep enough.
DMA controllers typically comprise three main control registers, a transfer length register, a source address register, and a destination address register. A different source address is associated with each of the serial devices. A destination address represents the address of the initial memory storage location for storing a grouping of serial device input data in the memory of the computer. A transfer length represents the total number of bytes to be transferred during a selected DMA operation. Thus, destination addresses along with corresponding transfer lengths define the destination locations in the processor s memory where various input data groupings are to be stored.
One typical application of a DMA controller is to connect the processor to a terminal having a keyboard as a serial source. In this application, the processor evaluates input data one character at a time. Another typical application of a DMA controller is to connect the processor to a serial channel which utilizes a higher level protocol such as one accommodating block transfers of a number of bytes. These bytes may include the destination address, commands, packet length data, and the like. In addition, the packets can be of variable length.
Currently, problems exist when using DMA controllers in both of the above applications. Existing DMA controllers define where to place a grouping of serial device input data based solely on a starting address stored in the destination address register and a defined transfer length stored in the transfer length register. Thus, when the processor initiates a conventional DMA operation, the processor is not informed of the receipt of any data from the serial channel until the number of bytes indicated by the defined transfer length are received indicating that the particular DMA operation is finished. However, a transfer length cannot be defined for data arriving from a keyboard because the processor does not know how many characters will be arriving. In addition, many protocols accommodating block transfers have data packets with variable packet lengths and existing DMA controllers cannot change the transfer length to adapt to the variable packet lengths because DMA controllers have defined transfer lengths. In both of these situations, the processor does not know that it has data in its memory that it should be processing.